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Feature/simplify masks #99
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what happens in the future when we get 256-element vectors? are masks just not supported?! |
I'm not sure. I'm still thinking about that. Unfortunately there's basically no way to represent that in the rust type system as far as generics go. Related to #50 |
An idea for fixing that: |
@programmerjake We will absolutely successfully work out a version that does not break on 2048-bit vectors with byte lanes before we stabilize anything (or else over my dead body, I suppose). You can expect to see this API change a lot, please do not read too much into any single version. Right now, we're trying things out a lot and seeing how things work. "How to handle masks on platforms" is definitely going to be an Unresolved Question in our RFC. |
I think there are two separate things here that we need to consider. One is that masks of any (reasonable) vector length should be supported, regardless of their implementation. That could be solved by using a trait like that (it may be appropriate as part of But I think there is a separate problem of explicitly exposing a mask as an integer bitmask. This is the SSE movemask example, where you use your bitmask as an index to a lookup table or similar. It's possible to have a 256-lane vector, but I don't think it's useful to expose an entire 256-bit "integer". Or, hypothetically, if we support Mask8<65536> in the future, I don't think there's any (portable!) way of exposing that. On AVX-512 is that 2048 k registers placed into an array in memory? I can't think of many (portable!) reasons you'd need to access that as a [u8]. This is what the |
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Anyone know why the MIPS masks seem to be reversed when packed to an integer? Somehow an LLVM bug or is there something peculiar about MIPS? |
IDK, but maybe it's related to Ada bit array ordering? |
...Ada bit array? |
They describe it some here: |
I think that leaves me with more questions than I started with. What do Ada arrays have to do with this? |
Well, when discussing which order to have bitmasks in SimpleV, lxo (one of the GCC Ada compiler engineers who's helping out with Libre-SOC) mentioned that Ada uses MSB to LSB ordering for bit arrays -- I figured that might be related since it uses the same order as what you apparently noticed in MIPS. |
Hmm. I'd hope that's not related to the problem. I would expect LLVM to maintain consistent bit field ordering across architectures. |
Can you rebase this, please? |
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Okay. "Simplify" might be a bit of a misnomer now (but the API is definitely simplified!) I used a Bit masks are now implemented as arrays of |
…e bitmask size. Improve bitmask to int conversion.
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This wound up not simplifying things as much as intended internally but it looks much better to me as an external API, really, which is what counts here. Can you add "modify Rust SIMD intrinsics to accept u8-or-something bitmasks" to #46 with a note about all the ones that need to get touched? |
Remove explicit bitmasks.
Add
ToBitMask
trait which allows you to convert masks tou64
.