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rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742
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Second this. |
@bors r+ |
☀️ Test successful - checks-actions |
What is this?This is an experimental post-merge analysis report that shows differences in test outcomes between the merged PR and its parent PR.Comparing 2196aff (parent) -> 85f518e (this PR) Test differencesNo test diffs found Job duration changes
How to interpret the job duration changes?Job durations can vary a lot, based on the actual runner instance |
Finished benchmarking commit (85f518e): comparison URL. Overall result: ❌ regressions - no action needed@rustbot label: -perf-regression Instruction countThis is the most reliable metric that we have; it was used to determine the overall result at the top of this comment. However, even this metric can sometimes exhibit noise.
Max RSS (memory usage)Results (primary -2.5%, secondary 2.3%)This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.
CyclesResults (secondary 5.5%)This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.
Binary sizeThis benchmark run did not return any relevant results for this metric. Bootstrap: 777.614s -> 776.851s (-0.10%) |
…, r=Amanieu rustc_target: RISC-V: add base `I`-related important extensions Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria: * Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or * Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and * Available on LLVM 18. This is based on [the latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications). LLVM Definitions: * [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137) * [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120) * [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124) * [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155) * [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144) Additional (1): One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`. Additional (2): In RISC-V, `G` is an abbreviation of following extensions: * `I` * `M` * `A` * `F` * `D` * `Zicsr` (although implied by `F`) * `Zifencei` and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly. Note: Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though). -------- This is the version 4. `Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`). Version 4: * Fixed some commit messages, * Added Android / VxWorks targets to imply `G` and * Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`) since rust-lang#138742 is now merged. Related: * rust-lang#44839 (`riscv_target_feature`) * rust-lang#114544 (This PR can be a prerequisite of resolving a part of that tracking issue) * rust-lang#138742 (Touches the same place and vector extensions depend on `Zicsr`) NOT Related but linked: * rust-lang#132618 (This PR won't be blocked by this issue since none of those extensions do not change the ABI) `@rustbot` r? `@Amanieu` `@rustbot` label +T-compiler +O-riscv +A-target-feature
Rollup merge of rust-lang#138823 - a4lg:riscv-feature-addition-base-i, r=Amanieu rustc_target: RISC-V: add base `I`-related important extensions Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria: * Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or * Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and * Available on LLVM 18. This is based on [the latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications). LLVM Definitions: * [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137) * [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120) * [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124) * [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155) * [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144) Additional (1): One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`. Additional (2): In RISC-V, `G` is an abbreviation of following extensions: * `I` * `M` * `A` * `F` * `D` * `Zicsr` (although implied by `F`) * `Zifencei` and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly. Note: Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though). -------- This is the version 4. `Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`). Version 4: * Fixed some commit messages, * Added Android / VxWorks targets to imply `G` and * Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`) since rust-lang#138742 is now merged. Related: * rust-lang#44839 (`riscv_target_feature`) * rust-lang#114544 (This PR can be a prerequisite of resolving a part of that tracking issue) * rust-lang#138742 (Touches the same place and vector extensions depend on `Zicsr`) NOT Related but linked: * rust-lang#132618 (This PR won't be blocked by this issue since none of those extensions do not change the ABI) `@rustbot` r? `@Amanieu` `@rustbot` label +T-compiler +O-riscv +A-target-feature
Currently, we have only unstable
v
target feature, but RISC-V have more vector-related extensions. The first commit of this PR adds them to unstableriscv_target_feature
.unaligned-vector-mem
: Has reasonably performant unaligned vectorunaligned-scalar-mem
target feature, but for vector instructions.zvfh
: Vector Extension for Half-Precision Floating-Pointzvfhmin
andzfhmin
zvfhmin
: Vector Extension for Minimal Half-Precision Floating-Pointzve32f
zve32x
,zve32f
,zve64x
,zve64f
,zve64d
: Vector Extensions for Embedded Processorszve32x
implieszvl32b
zve32f
implieszve32x
andf
zve64x
implieszve32x
andzvl64b
zve64f
implieszve32f
andzve64x
zve64d
implieszve64f
andd
v
implieszve64d
zvl*b
: Minimum Vector Length Standard Extensionszvl{N}b
implieszvl{N>>1}b
v
implieszvl128b
zvkb
: Vector Bit-manipulation used in Cryptographyzve32x
zvbb
: Vector basic bit-manipulation instructionszvkb
zvbc
: Vector Carryless Multiplicationzve64x
zvkg
: Vector GCM instructions for Cryptographyzve32x
zvkned
: Vector AES Encryption & Decryption (Single Round)zve32x
zvknha
: Vector SHA-2 (SHA-256 only))zve32x
zvknhb
: Vector SHA-2 (SHA-256 and SHA-512)zve64x
zvknha
, but doesn't imply that feature at least in LLVMzvksed
: SM4 Block Cipher Instructionszve32x
zvksh
: SM3 Hash Function Instructionszve32x
zvkt
: Vector Data-Independent Execution Latencyzkt
.zvkn
: Shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'zkn
.zvknc
: Shorthand for 'Zvkn' and 'Zvbc'zvkng
: shorthand for 'Zvkn' and 'Zvkg'zvks
: shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'zks
.zvksc
: shorthand for 'Zvks' and 'Zvbc'zvksg
: shorthand for 'Zvks' and 'Zvkg'Also, our vector ABI check wants
zvl*b
target features, the second commit of this PR updates vector ABI check to use them.rust/compiler/rustc_target/src/target_features.rs
Lines 707 to 708 in 4e2b096
r? @Amanieu
@rustbot label +O-riscv +A-target-feature