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rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742

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Merged
merged 2 commits into from
Mar 30, 2025
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rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742

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55add8f
rustc_target: Add more RISC-V vector-related features
taiki-e Mar 20, 2025
8a6f96a
rustc_target: Use zvl*b target features in vector ABI check
taiki-e Mar 20, 2025
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4 changes: 3 additions & 1 deletion compiler/rustc_codegen_llvm/src/llvm_util.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -274,7 +274,9 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
("arm", "fp16") => Some(LLVMFeature::new("fullfp16")),
// In LLVM 18, `unaligned-scalar-mem` was merged with `unaligned-vector-mem` into a single
// feature called `fast-unaligned-access`. In LLVM 19, it was split back out.
("riscv32" | "riscv64", "unaligned-scalar-mem") if get_version().0 == 18 => {
("riscv32" | "riscv64", "unaligned-scalar-mem" | "unaligned-vector-mem")
if get_version().0 == 18 =>
{
Some(LLVMFeature::new("fast-unaligned-access"))
}
// Filter out features that are not supported by the current LLVM version
Expand Down
54 changes: 51 additions & 3 deletions compiler/rustc_target/src/target_features.rs
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Expand Up @@ -497,7 +497,8 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
("m", Stable, &[]),
("relax", Unstable(sym::riscv_target_feature), &[]),
("unaligned-scalar-mem", Unstable(sym::riscv_target_feature), &[]),
("v", Unstable(sym::riscv_target_feature), &[]),
("unaligned-vector-mem", Unstable(sym::riscv_target_feature), &[]),
("v", Unstable(sym::riscv_target_feature), &["zvl128b", "zve64d"]),
("za128rs", Unstable(sym::riscv_target_feature), &[]),
("za64rs", Unstable(sym::riscv_target_feature), &[]),
("zaamo", Unstable(sym::riscv_target_feature), &[]),
Expand Down Expand Up @@ -529,6 +530,41 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
("zksed", Stable, &[]),
("zksh", Stable, &[]),
("zkt", Stable, &[]),
("zvbb", Unstable(sym::riscv_target_feature), &["zvkb"]),
("zvbc", Unstable(sym::riscv_target_feature), &["zve64x"]),
("zve32f", Unstable(sym::riscv_target_feature), &["zve32x", "f"]),
("zve32x", Unstable(sym::riscv_target_feature), &["zvl32b"]),
("zve64d", Unstable(sym::riscv_target_feature), &["zve64f", "d"]),
("zve64f", Unstable(sym::riscv_target_feature), &["zve32f", "zve64x"]),
("zve64x", Unstable(sym::riscv_target_feature), &["zve32x", "zvl64b"]),
("zvfh", Unstable(sym::riscv_target_feature), &["zvfhmin", "zfhmin"]),
("zvfhmin", Unstable(sym::riscv_target_feature), &["zve32f"]),
("zvkb", Unstable(sym::riscv_target_feature), &["zve32x"]),
("zvkg", Unstable(sym::riscv_target_feature), &["zve32x"]),
("zvkn", Unstable(sym::riscv_target_feature), &["zvkned", "zvknhb", "zvkb", "zvkt"]),
("zvknc", Unstable(sym::riscv_target_feature), &["zvkn", "zvbc"]),
("zvkned", Unstable(sym::riscv_target_feature), &["zve32x"]),
("zvkng", Unstable(sym::riscv_target_feature), &["zvkn", "zvkg"]),
("zvknha", Unstable(sym::riscv_target_feature), &["zve32x"]),
("zvknhb", Unstable(sym::riscv_target_feature), &["zve64x"]),
("zvks", Unstable(sym::riscv_target_feature), &["zvksed", "zvksh", "zvkb", "zvkt"]),
("zvksc", Unstable(sym::riscv_target_feature), &["zvks", "zvbc"]),
("zvksed", Unstable(sym::riscv_target_feature), &["zve32x"]),
("zvksg", Unstable(sym::riscv_target_feature), &["zvks", "zvkg"]),
("zvksh", Unstable(sym::riscv_target_feature), &["zve32x"]),
("zvkt", Unstable(sym::riscv_target_feature), &[]),
("zvl1024b", Unstable(sym::riscv_target_feature), &["zvl512b"]),
("zvl128b", Unstable(sym::riscv_target_feature), &["zvl64b"]),
("zvl16384b", Unstable(sym::riscv_target_feature), &["zvl8192b"]),
("zvl2048b", Unstable(sym::riscv_target_feature), &["zvl1024b"]),
("zvl256b", Unstable(sym::riscv_target_feature), &["zvl128b"]),
("zvl32768b", Unstable(sym::riscv_target_feature), &["zvl16384b"]),
("zvl32b", Unstable(sym::riscv_target_feature), &[]),
("zvl4096b", Unstable(sym::riscv_target_feature), &["zvl2048b"]),
("zvl512b", Unstable(sym::riscv_target_feature), &["zvl256b"]),
("zvl64b", Unstable(sym::riscv_target_feature), &["zvl32b"]),
("zvl65536b", Unstable(sym::riscv_target_feature), &["zvl32768b"]),
("zvl8192b", Unstable(sym::riscv_target_feature), &["zvl4096b"]),
// tidy-alphabetical-end
];

Expand Down Expand Up @@ -704,8 +740,20 @@ const ARM_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(1
const POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "altivec")];
const WASM_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "simd128")];
const S390X_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "vector")];
const RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] =
&[/*(64, "zvl64b"), */ (128, "v")];
const RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[
(32, "zvl32b"),
(64, "zvl64b"),
(128, "zvl128b"),
(256, "zvl256b"),
(512, "zvl512b"),
(1024, "zvl1024b"),
(2048, "zvl2048b"),
(4096, "zvl4096b"),
(8192, "zvl8192b"),
(16384, "zvl16384b"),
(32768, "zvl32768b"),
(65536, "zvl65536b"),
];
// Always warn on SPARC, as the necessary target features cannot be enabled in Rust at the moment.
const SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[/*(64, "vis")*/];

Expand Down
38 changes: 37 additions & 1 deletion tests/ui/check-cfg/target_feature.stderr
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Expand Up @@ -245,6 +245,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
`trustzone`
`ual`
`unaligned-scalar-mem`
`unaligned-vector-mem`
`v`
`v5te`
`v6`
Expand Down Expand Up @@ -325,7 +326,42 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
`zkr`
`zks`
`zksed`
`zksh`, and `zkt`
`zksh`
`zkt`
`zvbb`
`zvbc`
`zve32f`
`zve32x`
`zve64d`
`zve64f`
`zve64x`
`zvfh`
`zvfhmin`
`zvkb`
`zvkg`
`zvkn`
`zvknc`
`zvkned`
`zvkng`
`zvknha`
`zvknhb`
`zvks`
`zvksc`
`zvksed`
`zvksg`
`zvksh`
`zvkt`
`zvl1024b`
`zvl128b`
`zvl16384b`
`zvl2048b`
`zvl256b`
`zvl32768b`
`zvl32b`
`zvl4096b`
`zvl512b`
`zvl64b`
`zvl65536b`, and `zvl8192b`
= note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
= note: `#[warn(unexpected_cfgs)]` on by default

Expand Down
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