RISC-V: Add vector support#435
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The performance estimate after the split heuristic runs another binary
search (`optimize_binsearch`), which raises `SlothyException` on failure
rather than returning `success=False`. That exception propagated up and
discarded the already-optimized code. It also inherited the optimization
timeout, so a too-short timeout would abort it.
Catch the exception (warn and keep the optimized code without a stall
estimate) and disable the timeout for the estimate, since it only inserts
stalls into the already-fixed ordering.
…rce LMUL=1), unfold ntt_kyber example and add multiple optimization regions (vsetvli/ lmul problem), linting
…er_ntt2normal_order_rvv_vlen128
…ts. Add lmul value to more examples.
…fter optimization. wip: make vsetvl* write to CSR regs and vector instructions read from it to prevent wrong scheduling
- kyber_poly_reduce_rvv_vlen128_opt_c908.s: .globl exported the naive symbol instead of ..._opt_c908 (local label unreachable), and a malformed opcode 'bltua0, t4, ...' (missing space) failed to assemble. - kyber_poly_tomont_rvv_vlen128_opt_c908.s: same .globl export bug. These block linking the optimized RVV kernels into the pqrv kyber-poly-reduce test. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The SLOTHY-generated *_opt_c908.s files declared .globl with the naive symbol name instead of the ..._opt_c908 label, leaving the optimized entry point local (unreachable by the linker). Needed to link the optimized sampling kernels alongside the naive ones in the pqrv kyber-sampling test. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The re-optimized _dual_opt_c908 outputs had two mechanical defects: - .global declared poly_<fn>_opt_c908_dual while the entry label was the naive name poly_<fn>_rv64im_dual -> intended opt symbol undefined. Renamed both to poly_<fn>_rv64im_dual_opt_c908 (matches filename + test header). - mangled branch 'bnet4, zero, ...' -> 'bne t4, zero, ...'. They now assemble and link, but still SEGFAULT at run time (the software- pipelined store loop overruns the 256-coefficient output) -- the SLOTHY schedule itself needs fixing. Excluded from the executed pqrv test. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
1. RISCVVectorWidenExtend (vsext.vf2/vzext.vf2): the destination expands to an LMUL register group but the source was left unconstrained, so the allocator could place the source on the LOW register of the destination group (e.g. 'vsext.vf2 v18,v18' at LMUL=2). For a widening op (dest EEW > src EEW) RVV only permits the source to overlap the HIGHEST-numbered destination part, so the low overlap is illegal and traps on a spec-compliant core. Added args_in_out_different = [(0, 0)] (source disjoint from the dest group), mirroring the vrgather/vcompress handling. 2. AddiLoop.end(): the compare-and-branch for loops with an end register was emitted as two concatenated f-strings where the first lacked a trailing space -> 'bne'+'t4' = 'bnet4', and the comma before the label was missing. Added the space and comma. (bnez-style loops used the already-correct path.) Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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Adds support for the RISC-V "V"-Extension v1.0-rc1.