RISC-V: Add vector support

Makefile

@@ -0,0 +1,20 @@
+# Makefile for formatting and linting Python code
+
+# Targets
+.PHONY: black flake8 check all
+
+# Format code using black
+black:
+	black --version
+	black . --exclude venv
+
+# Lint code using flake8
+flake8:
+	flake8 --version
+	flake8 . --config .flake8 --exclude venv,.venv
+
+# Run both format and lint
+check: black flake8
+
+# Alias for check
+all: check

example.py

@@ -101,6 +101,10 @@
     example_instances as example_instances_riscv_kyber_basemul,
 )
 
+from examples.naive.riscv.kyber_sampling._example import (
+    example_instances as example_instances_riscv_kyber_sampling
+)
+
 from examples.naive.riscv.keccak._example import (
     example_instances as example_instances_riscv_keccak,
 )
@@ -125,6 +129,7 @@ def main():
         + example_instances_riscv_dilithium_basemul
         + example_instances_riscv_ntt_kyber
         + example_instances_riscv_kyber_basemul
+        + example_instances_riscv_kyber_sampling
         + example_instances_riscv_keccak
     )
 

examples/naive/riscv/dilithium_basemul/_example.py

@@ -154,6 +154,70 @@ def core(self, slothy):
         slothy.optimize_loop("poly_reduce_rv64im_loop")
 
 
+class RISC_V_poly_basemul_rvv_vlen128(OptimizationRunner):
+    def __init__(self, var="", arch=RISC_V, target=Target_XuanTieC908, timeout=None):
+        name = "dilithium_poly_basemul_rvv_vlen128"
+        infile = name
+
+        super().__init__(
+            infile,
+            name,
+            subfolder=SUBFOLDER,
+            rename=True,
+            arch=arch,
+            target=target,
+            timeout=timeout,
+            funcname="poly_basemul_rvv_vlen128",
+            var=var,
+        )
+
+    def core(self, slothy):
+        slothy.config.variable_size = True
+        slothy.config.constraints.stalls_first_attempt = 32
+        slothy.config.inputs_are_outputs = True
+
+        import slothy.targets.riscv.xuantie_c908 as target_module
+        target_module.lmul = 8
+        target_module.sew = 32
+
+        r = slothy.config.reserved_regs
+        r += ["x3"]
+        slothy.config.reserved_regs = r
+        slothy.config.outputs = ["x3"]
+        slothy.optimize_loop("poly_basemul_rvv_vlen128_loop")
+
+
+class RISC_V_poly_basemul_acc_rvv_vlen128(OptimizationRunner):
+    def __init__(self, var="", arch=RISC_V, target=Target_XuanTieC908, timeout=None):
+        name = "dilithium_poly_basemul_acc_rvv_vlen128"
+        infile = name
+
+        super().__init__(
+            infile,
+            name,
+            subfolder=SUBFOLDER,
+            rename=True,
+            arch=arch,
+            target=target,
+            timeout=timeout,
+            funcname="poly_basemul_acc_rvv_vlen128",
+            var=var,
+        )
+
+    def core(self, slothy):
+        slothy.config.variable_size = True
+        slothy.config.constraints.stalls_first_attempt = 32
+        slothy.config.inputs_are_outputs = True
+        import slothy.targets.riscv.xuantie_c908 as target_module
+        target_module.lmul = 8
+        target_module.sew = 32
+        r = slothy.config.reserved_regs
+        r += ["x3"]
+        slothy.config.reserved_regs = r
+        slothy.config.outputs = ["x3"]
+        slothy.optimize_loop("poly_basemul_acc_rvv_vlen128_loop")
+
+
 example_instances = [
     RISC_V_poly_basemul_8l_init_rv64im(),
     RISC_V_poly_basemul_8l_rv64im(),
@@ -165,4 +229,7 @@ def core(self, slothy):
     RISC_V_poly_basemul_8l_acc_rv64im(var="dual"),
     RISC_V_poly_basemul_8l_acc_end_rv64im(var="dual"),
     RISC_V_poly_reduce_rv64im(var="dual"),
+    # RVV
+    RISC_V_poly_basemul_rvv_vlen128(),
+    RISC_V_poly_basemul_acc_rvv_vlen128(),
 ]