Add autoinst_multidim_rename test and fix for issue #1848

[techdude]

I had some more time to look into this, and I have both a test case and a fix for the issue. The summary of the changes are as follows:

• Set vl-bits without the logic that prevents displaying it in certain circumstances. This ensures it has the correct value when used in the multi-dim hint comment, as well as ensuring it will have the correct value if the user uses it directly in an @"(...)" expression.
• Added variable auto-inst-vector for the auto-inst-vector component that can be masked if verilog-auto-inst-vector isn't t or 'unsigned and the net is signed, or if the port name matches one of the moddecls names (typically wires or outputs on the parent module) and the dimensions match. This preserves the original behavior expected by verilog-auto-inst-vector.
• In addition, if a port is connected to a different net (via an AUTO_TEMPLATE), then the name after renaming is used for the check (result is in auto-inst-vector-tpl). This ensures that AUTOWIRE/AUTOINPUT/AUTOOUTPUT works correctly for connections within a block, but it matches the expected behavior if the output port/wire already exists.

[wsnyder]

Thanks - merged manually to fix some spacing issues.