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Add autoinst_multidim_rename test and fix for issue #1848 #1850

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Add autoinst_multidim_rename test and fix for issue #1848 #1850

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4b937c2
Add autoinst_multidim_rename test and fix for issue #1848
Dec 8, 2023
2666f83
Add local bindings for new local variables
Dec 8, 2023
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44 changes: 44 additions & 0 deletions tests/autoinst_multidim_rename.sv
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Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
module parent(/*AUTOARG*/);
input [31:0][7:0] data_in;
output [4:0] meta_out;
output [4:0] meta_out_no_rename;
output [31:0][7:0] data_out;

/*AUTOWIRE*/

/* child1 AUTO_TEMPLATE (
.data_out (child1_out[][]),
.meta_out (child1_meta_out[]),
); */
child1 U1 (
/*AUTOINST*/
)

/* child2 AUTO_TEMPLATE (
.data_in (child1_out[][]),
.meta_in (child1_meta_out[]),
); */
child2 U2 (
/*AUTOINST*/
)

endmodule

module child1(/*AUTOARG*/);
input [31:0][7:0] data_in;
output [31:0][7:0] data_out;
output [4:0] meta_out;

endmodule

module child2(/*AUTOARG*/);
input [31:0][7:0] data_in;
input [4:0] meta_in;
output [31:0][7:0] data_out;
output [4:0] meta_out_no_rename;

endmodule

// Local Variables:
// verilog-auto-inst-vector:nil
// End:
72 changes: 72 additions & 0 deletions tests_ok/autoinst_multidim_rename.sv
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@@ -0,0 +1,72 @@
module parent(/*AUTOARG*/
// Outputs
meta_out, meta_out_no_rename, data_out,
// Inputs
data_in
);
input [31:0][7:0] data_in;
output [4:0] meta_out;
output [4:0] meta_out_no_rename;
output [31:0][7:0] data_out;

/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] child1_meta_out; // From U1 of child1.v
wire [31:0] [7:0] child1_out; // From U1 of child1.v
// End of automatics

/* child1 AUTO_TEMPLATE (
.data_out (child1_out[][]),
.meta_out (child1_meta_out[]),
); */
child1 U1 (
/*AUTOINST*/
// Outputs
.data_out (child1_out/*[31:0][7:0]*/), // Templated
.meta_out (child1_meta_out[4:0]), // Templated
// Inputs
.data_in (data_in/*[31:0][7:0]*/));

/* child2 AUTO_TEMPLATE (
.data_in (child1_out[][]),
.meta_in (child1_meta_out[]),
) */
child2 U2 (
/*AUTOINST*/
// Outputs
.data_out (data_out/*[31:0][7:0]*/),
.meta_out_no_rename (meta_out_no_rename),
// Inputs
.data_in (child1_out/*[31:0][7:0]*/), // Templated
.meta_in (child1_meta_out[4:0])); // Templated

endmodule

module child1(/*AUTOARG*/
// Outputs
data_out, meta_out,
// Inputs
data_in
)
input [31:0][7:0] data_in;
output [31:0][7:0] data_out;
output [4:0] meta_out;

endmodule

module child2(/*AUTOARG*/
// Outputs
data_out, meta_out_no_rename,
// Inputs
data_in, meta_in
);
input [31:0][7:0] data_in;
input [4:0] meta_in;
output [31:0][7:0] data_out;
output [4:0] meta_out_no_rename;

endmodule

// Local Variables:
// verilog-auto-inst-vector:nil
// End:
38 changes: 26 additions & 12 deletions verilog-mode.el
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Expand Up @@ -12256,15 +12256,9 @@ If PAR-VALUES replace final strings with these parameter values."
(vl-memory (verilog-sig-memory port-st))
(vl-mbits (if (verilog-sig-multidim port-st)
(verilog-sig-multidim-string port-st) ""))
(vl-bits (if (or (eq verilog-auto-inst-vector t)
(and (eq verilog-auto-inst-vector `unsigned)
(not (verilog-sig-signed port-st)))
(not (assoc port (verilog-decls-get-signals moddecls)))
(not (equal (verilog-sig-bits port-st)
(verilog-sig-bits
(assoc port (verilog-decls-get-signals moddecls))))))
(or (verilog-sig-bits port-st) "")
""))
(vl-bits (or (verilog-sig-bits port-st) ""))
(auto-inst-vector nil)
(auto-inst-vector-tpl nil)
(case-fold-search nil)
(check-values par-values)
tpl-net dflt-bits)
Expand All @@ -12290,16 +12284,26 @@ If PAR-VALUES replace final strings with these parameter values."
vl-mbits (verilog-simplify-range-expression vl-mbits)
vl-memory (when vl-memory (verilog-simplify-range-expression vl-memory))
vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
(setq auto-inst-vector
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(if (or (eq verilog-auto-inst-vector t)
(and (eq verilog-auto-inst-vector `unsigned)
(not (verilog-sig-signed port-st)))
(not (assoc port (verilog-decls-get-signals moddecls)))
(not (equal (verilog-sig-bits port-st)
(verilog-sig-bits (assoc port (verilog-decls-get-signals moddecls))))))
vl-bits
""))
;; Default net value if not found
(setq dflt-bits (if (or (and (verilog-sig-bits port-st)
(setq
dflt-bits (if (or (and (verilog-sig-bits port-st)
(verilog-sig-multidim port-st))
(verilog-sig-memory port-st))
(concat "/*" vl-mbits vl-bits
;; .[ used to separate packed from unpacked
(if vl-memory "." "")
(if vl-memory vl-memory "")
"*/")
(concat vl-bits))
(concat auto-inst-vector))
tpl-net (concat port
(if (and vl-modport
;; .modport cannot be added if attachment is
Expand Down Expand Up @@ -12338,10 +12342,20 @@ If PAR-VALUES replace final strings with these parameter values."
(if (numberp value) (setq value (number-to-string value)))
value))
(substring tpl-net (match-end 0))))))
;; Get range based off template net
(setq auto-inst-vector-tpl
(if (or (eq verilog-auto-inst-vector t)
(and (eq verilog-auto-inst-vector `unsigned)
(not (verilog-sig-signed port-st)))
(not (assoc tpl-net (verilog-decls-get-signals moddecls)))
(not (equal (verilog-sig-bits port-st)
(verilog-sig-bits (assoc tpl-net (verilog-decls-get-signals moddecls))))))
vl-bits
""))
;; Replace @ and [] magic variables in final output
(setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
(setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
(setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
(setq tpl-net (verilog-string-replace-matches "\\[\\]" auto-inst-vector-tpl nil nil tpl-net)))
;; Insert it
(when (or tpl-ass (not verilog-auto-inst-template-required))
(verilog--auto-inst-first indent-pt section)
Expand Down
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