Introduce MAX32660 SoC

boards/adi/max32660evsys/Kconfig.max32660evsys

@@ -0,0 +1,7 @@
+# MAX32660EVSYS boards configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX32660EVSYS
+	select SOC_MAX32660

boards/adi/max32660evsys/board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/adi/max32660evsys/board.yml

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: max32660evsys
+  full_name: MAX32660EVSYS
+  vendor: adi
+  socs:
+    - name: max32660

boards/adi/max32660evsys/doc/index.rst

@@ -0,0 +1,123 @@
+.. zephyr:board:: max32660evsys
+
+Overview
+********
+The MAX32660 evaluation system offers a compact development platform that
+provides access to all the features of the MAX32660 in a tiny, easy to
+use board. A MAX32625PICO-based debug adapter comes attached to the main
+board. It can be snapped free when programming is complete. The debug
+module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink
+functionality. Combined measurements are 0.65in x 2.2in, while the main board
+alone measures 0.65in x 0.95in. External connections terminate in a dual-row
+header footprint compatible with both thru-hole and SMT applications. This
+board provides a powerful processing subsystem in a very small space that
+can be easily integrated into a variety of applications.
+
+The Zephyr port is running on the MAX32660 MCU.
+
+Hardware
+********
+
+- MAX32660 MCU:
+
+  - High-Efficiency Microcontroller for Wearable Devices
+
+     - Internal Oscillator Operates Up to 96MHz
+     - 256KB Flash Memory
+     - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode
+     - 16KB Instruction Cache
+     - Memory Protection Unit (MPU)
+     - Low 1.1V VCORE Supply Voltage
+     - 3.6V GPIO Operating Range
+     - Internal LDO Provides Operation from Single Supply
+     - Wide Operating Temperature: -40°C to +105°C
+
+  - Power Management Maximizes Uptime for Battery Applications
+
+     - 85µA/MHz Active Executing from Flash
+     - 2µA Full Memory Retention Power in Backup Mode at VDD = 1.8V
+     - 450nA Ultra-Low Power RTC at VDD=1.8V
+     - Internal 80kHz Ring Oscillator
+
+  - Optimal Peripheral Mix Provides Platform Scalability
+
+     - Up to 14 General-Purpose I/O Pins
+     - Up to Two SPI
+     - I2S
+     - Up to Two UARTs
+     - Up to Two I2C, 3.4Mbps High Speed
+     - Four-Channel Standard DMA Controller
+     - Three 32-Bit Timers
+     - Watchdog Timer
+     - CMOS-Level 32.768kHz RTC Output
+
+- Benefits and Features of MAX32660-EVSYS:
+
+  - DIP Breakout Board
+
+     - 100mil Pitch Dual Inline Pin Headers
+     - Breadboard Compatible
+
+  - Integrated Peripherals
+
+     - Red Indicator LED
+     - User Pushbutton
+
+  - MAX32625PICO-Based Debug Adapter
+
+     - CMSIS-DAP SWD Debugger
+     - Virtual UART Console
+
+Supported Features
+==================
+
+The ``max32660evsys`` board supports the following interfaces:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| CLOCK     | on-chip    | clock and reset control             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial                              |
++-----------+------------+-------------------------------------+
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+An Arm® debug access port (DAP) provides an external interface for debugging during application
+development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial
+interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4).
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (J3) using an
+   appropriate adapter board and cable.
+
+Debugging
+=========
+
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `MAX32660EVSYS web page`_
+
+.. _MAX32660EVSYS web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32660-evsys.html

boards/adi/max32660evsys/max32660evsys.dts

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max32660.dtsi>
+#include <adi/max32/max32660-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices MAX32660EVSYS";
+	compatible = "adi,max32660evsys";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram2;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+	};
+
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_tx_p0_10 &uart1_rx_p0_11>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};

boards/adi/max32660evsys/max32660evsys.yaml

@@ -0,0 +1,13 @@
+identifier: max32660evsys
+name: max32660evsys
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - serial
+ram: 96
+flash: 256

boards/adi/max32660evsys/max32660evsys_defconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y

boards/common/openocd-adi-max32.boards.cmake

@@ -10,6 +10,8 @@ if(CONFIG_SOC_MAX32650)
   set(MAX32_TARGET_CFG "max32650.cfg")
 elseif(CONFIG_SOC_MAX32655_M4)
   set(MAX32_TARGET_CFG "max32655.cfg")
+elseif(CONFIG_SOC_MAX32660)
+  set(MAX32_TARGET_CFG "max32660.cfg")
 elseif(CONFIG_SOC_MAX32662)
   set(MAX32_TARGET_CFG "max32662.cfg")
 elseif(CONFIG_SOC_MAX32666)

dts/arm/adi/max32/max32660-pinctrl.dtsi

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+			/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_0: spi1_miso_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_0: uart1_tx_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_1: spi1_mosi_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_1: uart1_rx_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p0_2: i2c1_scl_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_2: spi1_sck_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ cal32k_p0_2: cal32k_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p0_3: i2c1_sda_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_3: spi1_ss0_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_3: tmr0_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_tx_p0_4: uart0_tx_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_cts_p0_6: uart0_cts_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_6: uart1_tx_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_7: spi0_ss0_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_rts_p0_7: uart0_rts_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_7: uart1_rx_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p0_8: i2c0_scl_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ swdio_p0_8: swdio_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p0_9: i2c0_sda_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ swdclk_p0_9: swdclk_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_10: spi1_miso_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_10: uart1_tx_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_11: spi1_mosi_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_11: uart1_rx_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_12: spi1_sck_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_cts_p0_12: uart1_cts_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_rts_p0_13: uart1_rts_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+		};
+	};
+};