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Verilog: KNOWNBUG for declarations inside a named block inside a function #969

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Feb 6, 2025
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8 changes: 8 additions & 0 deletions regression/verilog/functioncall/named_block1.desc
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
KNOWNBUG
named_block1.sv

^\[.*\] always main\.foo\(\) == 123: PROVED$
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
13 changes: 13 additions & 0 deletions regression/verilog/functioncall/named_block1.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
module main;

function [31:0] foo;
begin : block_name
reg [31:0] x;
x = 123;
foo = x;
end
endfunction;

assert final (foo() == 123);

endmodule
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